The present invention relates to logic circuits and semiconductor integrated circuit device, and, more particularly, relates to arts especially effective for use in such circuits as Non Threshold Logic (hereinafter referred to as NTL) circuit, Super Push-pull Logic (hereinafter referred to as SPL) circuit, and Emitter Coupled Logic (hereinafter referred to as ECL) circuit and, further, in high-speed logical integrated circuit device with the above mentioned logic circuits employed as their basic constituents.
There is an NTL circuit receiving a digital input signal of a relatively small amplitude for performing high-speed logical operations. Also, there is a high-speed logical integrated circuit device with such NTL circuit used as its basic constituent and, further, a high-speed computer constituted of such high-speed logical integrated circuit device.
The NTL circuit includes, as illustrated in FIG. 21, a phase divider circuit formed of a bipolar transistor (hereinafter briefly referred to as "transistor") T1 receiving an input signal VI and its collector resistor R1 and emitter resistor R2 and, further, includes an output emitter-follower circuit for transmitting an inverted output signal of the phase divider circuit, i.e., the collector voltage Vc of the transistor T1, as an output signal VO of the circuit. In the NTL circuit, the input signal VI and output signal VO are set to have a relatively low amplitude as, for example, 0.6 V. As a result, the time required for charging and discharging the stray capacitance of each node or load capacitance is decreased and, accordingly, high-speed operation of the circuit as logic circuit can be attained.
In such NTL circuit, when the input signal VI is changed to the low level and the output signal VO is changed to the high level, the output-load capacitance C.sub.L coupled with the output terminal is actively charged through the output transistor T2. Hence, the change to the high level of the output signal VO is speeded up and, thus, the transmission delay time of the change to the low level of the input signal VI to the logic circuit is shortened. However, when the input signal VI is changed to the high level and the output signal VO is changed to the low level, the output-load capacitance C.sub.L is passively discharged through the emitter resistor R4 of the output transistor T2. As a result, the change of the output signal VO to the low level is delayed according to the time constant determined by the electrostatic capacity of the output-load capacitance C.sub.L and the resistance of the resistor R4. Thus, the transmission delay time of the change to the high level of the input signal VI to the logic circuit is prolonged.
To overcome such difficulty, the inventors, prior to the present invention, developed a so-called SPL circuit, which was obtained by replacing the resistor R4 in the above described NTL circuit with an active pull-down circuit, and finished the application for a patent for that invention.
The SPL circuit, as illustrated in FIG. 22, includes an active pull-down circuit having, in its center, a transistor T6 provided as the emitter load for an output transistor T5. The transistor T6 is supplied with a bias voltage of a value immediately before the voltage bringing the same into the on state, from a bias circuit formed of a transistor T4 and a resistor R7. Further, the base of the transistor T6 is supplied with the differential signal of the noninverted output signal of the phase divider circuit through a differential circuit formed of a capacitor C2 and the resistor R7. Thereby, the transistor T6 is temporarily turned on at the beginning of the change of the input signal VI to go high and the output-load capacitance C.sub.L is actively discharged through the transistor T6. As a result, the change of the output signal VO to go low is speeded up and the transmission delay time of the change going to the high level of the input signal VI to the logic circuit is shortened. Further, since the transistor T6 as the emitter load of the transistor T5 is normally held off and turned on temporarily only at the beginning of the change of the input signal VI to go high, the power consumption of the logic circuit can be extremely reduced.
As to the NTL circuit, there is a description, for example, in Japanese Laid-open Patent Publication No. 63-124615, and as to the SPL circuit, there are descriptions in the specification of patent application Ser. No. 330,461, filed in the U.S. Patent Office on Mar. 30, 1989, which issued on Mar. 12, 1991 into U.S. Pat. No. 4,999,520, and in the specification of continuation-in-part application Ser. No. 557,109, filed in the U.S. Patent Office on Jul. 25, 1990.